The present invention relates to the field of forming CMOS integrated circuits, in particular the gate electrode of a CMOS transistor. More particularly, the present invention relates to a double exposure double etch method for forming the gate electrode.
There is a strong drive for designers to shrink dimensions of CMOS integrated circuits. The advantages of smaller dimensions include more logic gates per area for more functionality, faster device speed, hence faster overall circuit speed and lower manufacturing cost per function. These advantages will continue to drive a need to shrink dimensions. At the present time, virtually all semiconductor manufacturing use optical lithographic methods, with exposure wavelengths as short as 193 nm.
As dimensions in integrated circuits have shrunk down to the limits of resolution of current lithographic technology, many attempts have been made to circumvent the resolution limitations of optical lithography.
In current technology, a CMOS integrated circuit is built up from a number of pattern layers, most of which are not relevant to the current invention. One of the most critical pattern layers that is important to the present invention defines the transistor gates, hereinafter referred to as just gates. It is well known that control of the transistor gate area is crucial to the attainment of high speed circuitry. In particular, linewidth deviations of the gates will cause transistor speed deviations which will disrupt the desired overall circuit timing and performance.
In semiconductor processing today, the gates are built by an advanced process called double exposure double etch which is illustrated in FIGS. 1 through 4. FIG. 1 illustrates the layout design of the gates 10. The linewidth of the gates 10 is a critical dimension which must be accurately controlled. The gates 10 are separated by gap 12. The dimension of gap 12 is a noncritical dimension. To achieve the layout design shown in FIG. 1, two separate lithographic processes are required. As shown in FIGS. 2A and 2B, there is first a gate lithographic process in FIG. 2A which defines the gate lines 14 and then a second so-called cut lithographic process in FIG. 2B which cuts the gate lines 14 at gate cut areas 16. By a Boolean addition of the gate lithographic process shown in FIG. 2A and the cut lithographic process shown in FIG. 2B, the overall lithographic process is illustrated in FIG. 3. It can be seen that where the gate cut areas 16 intersect with gate lines 14, gates 10 are formed. The final structure is shown in FIG. 4.
Referring back to FIG. 3, there are areas 18 which may be called overlap areas. What is meant by overlap areas is that the gate layer is first etched between the gate lines 14 and then the gate layer is etched again across the gate lines 14 to form gate cut areas 16. The overlap areas 18 are actually etched twice—once when the gate lines 14 are formed and then again when the gate cut areas 16 are formed. This double etching can lead to so-called punch through areas into the underlying silicon or shallow trench isolation (STI) areas by the following process. The overlapped area 18 is etched more into the gate layer (usually doped polysilicon) than either of the cut areas 16 or the areas between the gates 14. With each subsequent etching step into the metal gate layer and then any underlying layer such as a high dielectric constant dielectric layer (“high K layer”), the overlapped area 18 will always etch deeper. Ideally, the process should stop on the last layer which is the silicon layer or STI layer. But, since the overlap area 18 always etches ahead of the cut areas 16 and the areas between the gates 14, the overlap area may actually etch into the silicon layer or STI layer which is called punch through. Punch through is to be avoided.
The present inventors have recognized that the punch through problem is exacerbated by the difference in topography between the gate stack area and the STI area. This is illustrated in FIG. 5A for current state of the art semiconductors and FIG. 5B for advanced semiconductors. For purposes of the illustration in FIG. 5A, gate layer 20 is located at a different level than STI area 22. The bulk silicon is reference number 38. The difference in height 24 is called the RX topography. It should be understood that it is also possible that the STI area 22 could be at a higher level than the gate layer 20. Also shown in FIG. 5A is a hard mask 26 in conjunction with an organic planarizing layer 32 (called an “OPL” in the art) which are used to make the cut areas 16 (shown in FIGS. 3 and 4). According to current process guidelines, the OPL is etched in the cut areas 16 as indicated by 28 but some OPL is left, as indicated by 30, in the up area (i.e., the gate layer 20) so that the gate layer 20 is not actually etched in this process step. However, when progressing to FIG. 5B for advanced semiconductors, it can be seen that the hardmask 26 is thinner because of the requirement for thinner gate lines and to avoid overshadowing. Consequently, the OPL etching, as indicated by 34, etches into the gate layer 20 in the up area by an amount indicated by 36. Such etching into the up area (i.e., the gate layer 20 as shown in FIG. 5B) eventually leads to punch through in the overlap area 18.
The double exposure double etch process has been proposed by others as described above. Another example of a double exposure double etch process is disclosed in Brunner et al. U.S. Patent Application Publication US 2007/0212863, the disclosure of which is incorporated by reference herein.
There has also been proposed a double exposure single etch process in order to work around the present day limitations of optical lithography. Some examples of double exposure, single etch are disclosed in Chang U.S. Patent Application Publication US 2008/0032508 and Lalbahadoersing et al. U.S. Patent Application Publication US 2007/0212648, the disclosures of which are incorporated by reference herein. However, these references do not disclose the Boolean addition of gate and cut lithographic processes to arrive at a critically dimensioned gate.